1. Field of the Invention
The invention relates to design of tests that are used in simulation of design(s) of circuits. More specifically, the invention relates to a method and an apparatus for automatically increasing functional coverage in stimulus driven simulation of the circuit designs that are typically implemented in integrated circuit (IC) chips.
2. Related Art
In the design of integrated circuit (IC) chips, it is common to test IC designs by use of a testbench. A test bench in a high-level verification language (HVL) environment includes test generators that randomly generate input signals for the IC design. U.S. Pat. No. 6,141,630 granted to McNamara, et al. on Oct. 31, 2000 entitled “System and method for automated design verification” is incorporated by reference herein in its entirety as background. This patent describes a coverage analysis tool (see FIG. 1A attached hereto) which monitors output data from a simulated design and identifies portions of the simulated design that remain to be tested. The coverage analysis tool updates a coverage database. A test generator is coupled to the IC design database and the coverage database. The test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. The simulated design includes software, expressed in Verilog or VHDL which is executed within a computer to model the operational characteristics of the circuit being designed.
Values of test vectors may be generated randomly in the belief that events of interest to the user will eventually occur as simulation progresses over time. However, there is no guarantee that such events will in fact occur during a limited duration within which simulation is performed, or that such events will occur even if the simulation duration is infinitely long. Some prior art testbenches generate test vectors (each vector containing a set of values of stimulus signals) independent of (i.e. without reference to) the events of interest specified by the user. If any user-specified events do not occur during simulation, the user laboriously creates additional values for the stimulus signals (either manually or by specifying additional directives to test generators) to attempt to achieve coverage of any events that have not yet occurred (also called “holes”).
An article entitled “Hole Analysis for Functional Coverage Data” by Oded Lachish, et al. presented at the Design Automation Conference (DAC) Jun. 10-14, 2002 is incorporated by reference herein in its entirety as background. This article describes as a first step, a need for the user to model restrictions. As examples of user-supplied restrictions, this article shows (see FIG. 1B attached hereto) combinations of attribute values that should never occur. Next, after coverage of tests has been measured, this article describes performance of a method called “hole analysis” for discovering and reporting large uncovered spaces for cross-product functional coverage models. In a cross-product functional coverage model, the list of coverage tasks comprises all possible combinations of values for a given set of attributes. According to this article, hole analysis groups together sets of uncovered tasks that share some common properties, thus allowing the coverage tool to provide shorter and more meaningful coverage reports to the user. As an example, this article states that it is much more informative to report that a “reject” response never occurred, than it is to include all possible cases of a request with a “reject” response in the list of uncovered tasks.
This article by Oded Lachish, et al. further teaches aggregating together any two holes whose Hamming distance is one. Thus, two uncovered tasks <0,2> and <0,3> are aggregated into a single hole <0,{2,3}>. The article notes that Hamming distances can be also computed on aggregated holes and that the distance between any two holes is equal to the number of differing attributes, but now the comparison is done for aggregated sets as well as atomic values. The article states that the process can be applied iteratively until no more new aggregated holes are discovered. FIG. 1C (attached hereto) shows how the five tasks <0,2>, <0,3>, <7,2>, <7,3>, and <7,4> can be aggregated together until only the holes <{0,7}, {2,3}> and <7, {2,3,4}> remain.
The above-described article by Oded Lachish, et al. further describes one objective of hole analysis as finding projected holes of highest dimensionality. The article defines dimensionality as follows “Any coverage model of n attributes can be viewed as a set of tasks or points in an n-dimensional space.” The article further describes iterating over all potential holes, starting with those of the highest dimensionality, whereby any subspace that is unmarked is reported as a significant hole and its descendants are recursively marked. Finally, this article also states that the language used by their coverage tools to report holes is equivalent to the one used by the user for defining restrictions. One example provided in this article is that a hole <Arith,SNaN,*,*> is expressed by the restriction Instr ε Arith  Result≠SNaN. The article goes on to state: “This means that holes can be easily translated into restrictions if necessary. In many cases, the translation can be automated.”
An article entitled “Coverage Directed Test Generation for Functional Verification using Bayesian Networks” by Shai Fine and Avi Ziv presented at the Design Automation Conference (DAC) 2003 is also incorporated by reference herein in its entirety as background. This article describes a first step in which a training set is used to learn the parameters of a Bayesian network that models a relationship between coverage information and directives to test generators. In a second step, the Bayesian network is used to provide the most probable directives that would lead to a given coverage task (or set of tasks). Another article entitled “StressTest: An Automatic Approach to Test Generation Via Activity Monitors” presented by Ilya Wagner, Valeria Bertacco and Todd Austin, presented at the Design Automation Conference (DAC) Jun. 13-17, 2005 is incorporated by reference herein in its entirety as background. This article describes a tool called StressTest for automatically generating instructions to test a microprocessor design.
See also, yet another article entitled “Coverage-Driven Functional Verification” by Sharon Rosenberg and David Van Campenhout published in September 2001, available at following URL (wherein “/” is replaced by “%”):                http:%%www.verisity.com%resources%whitepaper%coverage_driven.html.Also see the article entitled “Functional Coverage Driven Test Generation for Validation of Pipelined Processors” by Prabhat Mishra and Nikil Dutt, published Mar. 12, 2004 as CECS Technical Report #04-05, by Center for Embedded Computer Systems, University of California, Irvine, Calif. Both these articles are also incorporated by reference herein in their entirety as background.        
Constraints on signals to be input to an IC design's simulation, as well as goals for coverage of such signals (“coverage goals”) during functional verification of the IC design may be manually specified in a hardware verification language (HVL) called “SYSTEMVERILOG” which is described in, for example, a document entitled “SystemVerilog 3.1a Language Reference Manual Accellera's Extensions to Verilog®” available at http:%%www.eda.org%sv%SystemVerilog—3.1a.pdf (wherein “/” is replaced by “%”), and this document is incorporated by reference herein in its entirety as background. An alternative HVL language is called OpenVera and is used by the VERA tool available from Synopsys, Inc. For more information on OpenVERA, see the book entitled “The Art of Verification with VERA” published September 2001 by Faisal Haque, Jonathan Michelson, and Khizar Khan that is incorporated by reference herein in its entirety. This book is available for purchase at http:%%www.verificationcentral.com%. Use of OpenVERA is also described in U.S. Pat. No. 6,925,617 that is incorporated by reference herein in its entirety, as background.